Conventionally, some of “RAM Built-in Self-Test (RAM-BIST)” circuits have the configuration that a plurality of RAM (Random Access Memory) macros have built-in BIST circuits on one-to-one correspondence basis to receive and give input and output data respectively. (Refer to an example shown in JP-A No. 111618/2000, FIG. 6.)
Also conventionally, it is observed that some configuration aimed at scaling down BIST circuits adopts a common part in the BIST circuit and designs data exchange with the data input and output circuits which are disposed in the proximity of the RAM macros and are dependent on the array arrangement of the RAM. (Refer to an example shown in JP-A No. 111618/2000, FIG. 1.)
Furthermore, also conventionally, some memory BIST in which CAM (Content Addressable Memory) is included is configured to exchange input and output data directly from the common BIST circuit to a plurality of memory macros including CAM. (Refer to an example shown in U.S. Pat. No. 5,535,164)
Generally, the methods to test the memory macros built in LSI (Large Scale Integration) chips include testing by means of external testing equipments and by means of BIST (Built-in Self-Test) circuit (hereinafter referred to as “RAM-BIST”) for testing RAM (Random Access Memory) macros.
The arithmetic pattern generator (hereinafter referred to as “APG”) of the conventional RAM-BIST has the function of selection among address initialization, increment, and decrement, and also among write data, expect data, and control signal. A selector allows selection of signals from the external pin input. As disclosed in JP-A No. 111618/2000, FIGS. 1 & 2, write data and expect data are given allocation of one-bit or two-bit signals that are to be allotted respectively to the even number bit and the odd number bit of the macro input/output data, thereby attaining the purpose of decreasing the number of wiring and creating required write data (A110/1 or patterns like stripes and checkerboard).
The configuration disclosed in U.S. Pat. No. 5,535,164 can be cited as an example of the idea of RAM-BIST applied to CAM (Content Addressable Memory). Specifically, the configuration is as mentioned below. As disclosed in FIG. 1, a common BIST circuit is provided corresponding to a plurality of memory macros including CAM and configured so as to exchange with respective macros such input and output signals as address signals, write/search data signals, control signals, expect data signals, and pass/fail signals. If a required type of signal is different with each macro, a proper type of signal is selected according to the control signal given to the BIST circuit.
When the BIST is to be applied to the testing of CAMs, testing the search operation of the CAM will require the BIST to be mounted with functions of creating data different from the RAM, such as to write different data for each address, and to write any one bit in high-level or low-level. In order to achieve the foregoing by means of the configuration disclosed in U.S. Pat. No. 5,535,164, it will be necessitated to enlarge the bit width for the data fed from the BIST circuit and supply as much write data as the data bit width of the CAM. Recently, however, the data width of the CAM is following the trend toward substantial increase. Therefore, in order to distribute signals from the APG to the CAM macros scattered around within the chip, increase is inevitably invited in the aspect of materials such as wiring channel region, buffer cells, flip-flop, etc., because data with a large bit width needs to be transferred. Further, in case equivalent test is made possible from LSI pins, too, the same number of pins as the bit width of the CAM data will be required. Because of the foregoing problems, mounting on the chip is considered difficult.
FIG. 9 shows an example of configuration of a semiconductor memory device having a BIST circuit based on the conventional technology. The device according to FIG. 9 includes: “a test pattern generator (APG) 101 of memory BIST”; “an external input signal terminal 102 for memory testing”; “testing circuit blocks 103A, 103D for CAM macros and the proximity thereof”; “testing circuit blocks 103B, 103C for RAM macros and the proximity thereof”; “pass/fail signals 17A, 17B, 17C, 17D, 17E, 17F, 17G, and 17H of each memory macro” which are the signals obtained after logical add [OR] is taken for each memory macro with respect to the output of the memory macro; “a test result check circuit 107” which receives input of the pass/fail signals from all the memory macros and give output on the result of the logical add [OR] thereof; and the output of the check circuit or the “pass/fail signal of all the memory macros 18.”
The testing circuit blocks 103A and 103D for CAM macros and the proximity thereof comprise “the tested CAM macros 105A, 105D, and 105E” that are shown in FIG. 9 as the CAM macros CAM1, CAM2, and CAM3 and “the comparator circuits 106A, 106B, 106E, 106F, 106G, and 106H to compare the output signals of the memory macros with expect data.”
The testing circuit blocks 103B and 103C for RAM macros and the proximity thereof comprise “the tested RAM macros 105B and 105C” shown as RAM macros RAM1 and RAM2 and “the comparator circuit 106C and 106D to compare the output signal of the memory macro with the expect data.”
Generally, the tested memory macros 105A, 105B, 105C, 105D, and 105E are different in size from one another and are placed in any location within the chip.
The address signal 11 and 12, write data signal 13A and 13B, and control signal 14 are distributed to the testing circuit blocks 103A, 103B, 103C, and 103D of each memory macro.
With reference to the signal distribution system from APG101 to the tested memory macros 105A, 105B, 105C, 105D, and 105E, FIG. 10 shows a schematic diagram illustrating the layout and wiring in the case that the block diagram shown in FIG. 9 is actually mounted on LSI chips. The selector to select test signals or signals from general logic, and also the output signal distribution system are omitted. The logic gate and wiring in the distribution system are not necessarily connected in the shortest distance, because these are mounted in the region not used in the general logic.
As an example, we now take a look at the number of input signals required for testing the macro 105A when the tested CAM macro 105A is of the 2048-word 576-bit structure. The write/search data signal 13A for the CAM macro is created in APG101 and distributed to the tested CAM macro 105A. Since the same number of signals as the bit width of data is required for the reason mentioned above, 576 signal lines are required to create a 576-bit data. Additional 11 signal lines are required for the address signal, and 3 lines for memory macro cell enable signals 15, one each for read, write and search; thus an aggregate total of 590 signal lines are to be distributed.
For the distribution of these signals, materials and space for wiring channel region, buffer, flip-flop, etc., are needed in abundance. Furthermore, in case equivalent test is made possible from LSI pins, too, as many pins as the bit width of the CAM data become necessary. In the foregoing example, at least 590 pins are necessary for input signals alone for the testing purpose. But if an over-2000-pin multi-pin package is used, it will result that more than half of the signal lines have to be allocated for the testing purpose, a level not practical at all.
As viewed above, chip mounting of the BIST for testing CAM macro will end up as extremely difficult on account of limitations in space, design complexity, and number of LSI pins. The present invention is intended to provide the means of enabling reduction in materials required for signal distribution and number of LSI pins in relation to data creation of the CAM macros as well as the means of facilitating mounting related circuits on chips.